A number of techniques have been proposed or suggested for containing power/leakage, improving performance, and extending scaling, including voltage islands, dynamic VDD, and separate supplies for logic and SRAM. For example, one commonly used technique drops the supply voltage (or raises the Ground voltage) through a metal oxide semiconductor (MOS) diode by one threshold voltage, VT. MOS diodes are also widely used in power-gating structures for logic and static random access memories (SRAM) to clamp the virtual VDD or virtual Ground (or both) to maintain adequate voltage across the memory elements for proper state retention, as illustrated in FIG. 1. FIG. 1 is a circuit diagram of a conventional CMOS circuit 100 having an integrated circuit 150, such as logic or memory elements, a power-gating switch 110 and a diode clamp 120.
It is desirable to have a variable VT diode to compensate for process variations, VT fluctuations or both. Furthermore, in SRAM applications, it is desirable to have a higher supply voltage during a read operation to maintain adequate noise margin, and a lower supply voltage during a write operation to facilitate writing. While well/body bias in bulk CMOS or PD/SOI devices have been proposed for used in modulating the threshold voltage, VT, the effect, in general, is quite limited. FIG. 2 is a schematic cross-section of a bulk-Si (or SOI) field effect transistor (FET) 200. As shown in FIG. 2, a large reverse well/body bias 220 causes an exponential increase in the reverse junction leakage including band-to-band tunneling current, while a forward well/body bias 210 results in an exponential increase in the forward diode leakage. Furthermore, it is known that the VT modulation effect diminishes with device scaling due to a low body factor in the scaled, low VT transistor. Finally, the distributed RC for the well/body contact limits the viable operating frequency.
E. Nowak et al., “Turning Silicon on its Edge,” IEEE Circuits Devices Mag. 20-31 (January/February, 2004), incorporated by reference herein, discloses a VT modulation technique that employs double-gate devices. The disclosed VT modulation technique uses asymmetrical gates, where the two gate electrodes consist of materials of differing work functions. FIG. 3 is a schematic cross-section of an asymmetrical double-gate nFET 300. As shown in FIG. 3, the front gate 310 typically uses n+ polysilicon and the back gate 320 typically consists of p+ polysilicon. For an asymmetrical pFET, a p+ polysilicon gate would be used for the front-gate and an n+ polysilicon gate would be used for the back-gate. In such an implementation, the predominant front-channel has a significantly lower VT and much larger current drive compared with the “weak” back-channel.
As shown in FIG. 3, the disclosed asymmetrical double-gate devices couple the front gate and back gate using a connection 330. The threshold voltage, VT, is a function of the fixed back gate voltage. Thus, the disclosed asymmetrical double-gate devices cannot be used to provide a variable VT diode and thereby control the virtual VDD or virtual Ground in the integrated circuit 100 of FIG. 1. A need exists for improved techniques for variable VT modulation. A further need exists for techniques for varying a supply voltage or a reference voltage (or both) using independently controlled asymmetrical double-gate devices.